The present invention relates to a magnetic memory device, and particularly to a configuration of an array of a magnetic memory device capable of implementing high-speed access without increasing an area occupied by a memory cell array.
As one of memory devices that store data therein on a non-volatile basis, there is known an MRAM (magnetic random access memory). The MRAM makes use of a variable magnetoresistive element for data storage. The variable magnetoresistive element has a TMR (tunneling magnetoresistive) element or an MTJ (magnetic tunneling junction) element. In either configuration, the variable magnetoresistive element has a fixed layer in which its direction of magnetization is fixed regardless of stored data, a free layer in which the direction of magnetization is set according to the stored data, and a barrier layer provided between the fixed layer and the free layer. When the free layer and the fixed layer coincide in magnetization direction with each other, an electrical resistance relative to the current that passes through the variable magnetoresistive element is small. On the other hand, when the free layer and the fixed layer are opposite in the magnetization direction, the electrical resistance becomes large. The magnitude of this resistance value is associated with data “0” and “1”.
The MRAM cell uses a data storage magneto-resistive effect. Thus, it is different from such a configuration that an electrical charge is stored in a floating gate or an insulating film as in a flash memory. There exists no limitation to the number of rewritings due to deterioration of an interlayer insulating film and the like. It is not necessary to perform the storage of an electrical charge into a charge storage layer (or insulating film) or its discharge upon data storage. The setting of a magnetization direction is simply performed. Since this magnetization inversion occurs in a short time, the writing of data can be performed at high speed.
When a processing system is built using such an MRAM, the MRAM needs to obtain high-speed access and reduce a layout area in terms of speeding-up of the whole system and its size reduction. In built-in applications such as SOC (System On Chip) in particular, there is a strong demand for a reduction in the layout area along with high-speed access.
A configuration for achieving a reduction in the layout area of a memory array for MRAM has been disclosed in a patent document 1 (Japanese Unexamined Patent Publication No. 2007-317948). In the configuration disclosed in the patent document 1, each MRAM cell comprises a series body of a magnetic memory transistor and a selection transistor. A source line for the selection transistor of each MRAM cell is shared by selection transistors of each adjacent row. A reduction in the layout area of each cell is achieved by sharing the source line between the adjacent cells.
A patent document 2 (Japanese Unexamined Patent Publication No. 2005-311132) discloses a configuration which achieves a reduction in variations in magnetic field at the writing of data into each MRAM cell. Namely, in the configuration disclosed in the patent document 2, selection transistors are disposed mirror-symmetrically so as to share a source line. On the other hand, upper wirings coupled to variable magnetoresistive elements are provided translation-symmetrically. With the translational symmetry, wirings lying above the selection transistors are disposed in a high density. Thus, the variable magnetoresistive elements are disposed at equal intervals and the proximity effect of the magnetic field is made uniform with respect to each variable magnetoresistive element, thereby reducing the variations in the magnetic field at the data writing.
A configuration for achieving the avoidance of crosstalk between wirings laid out in a high density has been disclosed in a patent document 3 (Japanese Unexamined Patent Publication No. 2002-270790). Also in the configuration shown in the patent document 3, selection transistors of MRAM cells are disposed mirror-symmetrically, and upper wirings relative to variable magnetoresistive elements are disposed translation-symmetrically. In the patent document 3, electrical current is caused to flow into a write word line adjacent to a selected row in the direction opposite to the write word line at the selected row upon the data writing, thereby avoiding miswriting to each adjacent cell.
A patent document 4 (Japanese Unexamined Patent Publication No. 2005-108973) has disclosed a configuration for achieving a reduction in crosstalk between wirings of a core/peripheral circuit section at an MRAM using TMR elements. In the configuration shown in the patent document 4, components for core/peripheral circuits and a memory array are formed by the same process. As to memory cells, upper wirings have translational symmetry and selection transistors are disposed mirror-symmetrically. In the core/peripheral circuit section, crosstalk where a dummy of the TMR element is disposed and a bit line and a write word line are disposed close to each other can be avoided by the dummy TMR element.
A configuration of a spin injection MRAM using spin injection in the MRAM has been disclosed in a patent document 5 (Japanese Unexamined Patent Publication No. 2006-54046) and a patent document 6 (Japanese Unexamined Patent Publication No. 2007-311514). The spin injection MRAM causes a write current to flow through a variable magnetoresistive element in the direction corresponding to the logical value of write data. The direction of magnetization of a free layer is set according to a spin deflection direction of the write current. Also in the configuration shown in the patent document 5, selection transistors of adjacent MRAM cells share a source region therefor and are disposed mirror-symmetrically.
In the patent document 6, the variable magnetoresistive element makes use of an N channel MOS transistor (insulated gate field effect transistor) or a P channel MOS transistor as a selection transistor depending on its coupling mode so as to suppress the influence of the threshold voltage of each selection transistor upon data writing. As to a write current, a write current at the time that rewriting is performed in a magnetizing anti-parallel direction is larger than a current required upon writing to a magnetizing parallel state. Upon this writing, the write current is caused to flow at source ground to thereby allow a large current to flow. Upon reading, the current is caused to flow in the same direction as upon writing to the anti-parallel state, thereby allowing a large current to flow upon the reading.